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MSC23S4641E-8BS16 (98.06.22) semiconductor MSC23S4641E-8BS16 4,194,304 word x 64 bit synchronous dynamic ram module (2bank): description the oki MSC23S4641E-8BS16 is a fully decoded, 4,194,304 x 64bit synchronous dynamic random access memory composed of sixteen 16mb drams(2mx8) in tsop packages mounted with decoupling capacitors on a 168-pin glass epoxy dual-in-line package supports any application where high density and large capacity of storage memory are required, like for example pcs or servers. features 4-meg word x 64-bit (2bank 8 byte) organization 168-pin dual inline memory module all dq pins have 10 w damping resister single 3.3v power supply, 0.3v tolerance input :lvttl compatible output :lvttl compatible refresh : 4,096 cycles/64 ms programmable data transfer mode ? cas latency (2, 3) ? burst length(1,2,4,8,full) ? data scramble(sequential,interleave) cbr auto-refresh, self-refresh capab ility serial presence detect (spd) with eeprom product organization product name operation access time(max.) frequency(max.) tac2 tac3 MSC23S4641E-8BS16 125mhz 10.0ns 6.0ns
MSC23S4641E-8BS16 (98.06.22) block diagram clk2 5 6 clk0 1 2 clk3 clk1 10 11 14 15 7 8 3 412 13 16 9 / cs0 cke0 dqmb0 dqmb1 dq0 dq7 dq0 dq7 dq8 dq15 dqmb4 dq0 dq7 dqm cke / cs dqm cke / cs dq40 dq47 dqmb5 dqmb2 dqmb3 dq0 dq7 dq16 dq23 dq0 dq7 dq24 dq31 dqmb7 dq0 dq7 dq48 dq55 dq0 dq7 dq56 dq63 dqm cke / cs dqm cke / cs dqm cke / cs dqm cke / cs / cs2 dqmb6 dq0 dq7 dqm cke / cs dq0 dq7 dqm cke / cs dq0 dq7 dqm cke / cs dq0 dq7 dqm cke / cs dq0 dq7 dqm cke / cs dq0 dq7 dqm cke / cs dq0 dq7 dqm cke / cs dq0 dq7 dqm cke / cs / cs1 / cs3 cke1 dq32 dq39 dq0 dq7 dqm cke / cs dq0 dq7 dqm cke / cs 10k w vcc vss two decoupling capacitors per sdram 0.1uf 0.33uf / ras,/cas,/we a0-a11 116 scl sda a0 a1 a2 sa0 sa1 sa2 serial pd 3.3pf 3.3pf wp 47k w 6 10 3 4 911 12 15 16 13 14 1 8 7 2 17 5 3.3pf 3.3pf note. the value of all resistors is 10 w expect wp and cke1 module outline (front) (back) 1 85 10 94 11 95 40 124 41 125 84 168
MSC23S4641E-8BS16 (98.06.22) pin configuration fr o nt s i de b ac k s i de fr o nt s i de b ac k s i de pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 vss 85 vss 43 vss 127 vss 2 dq0 86 dq32 44 n.c 128 cke0 3 dq1 87 dq33 45 /cs2 129 /cs3 4 dq2 88 dq34 46 dqmb2 130 dqmb6 5 dq3 89 dq35 47 dqmb3 131 dqmb7 6 vcc 90 vcc 48 n.c 132 n.c 7 dq4 91 dq36 49 vcc 133 vcc 8 dq5 92 dq37 50 n.c 134 n.c 9 dq6 93 dq38 51 n.c 135 n.c 10 dq7 94 dq39 52 n.c 136 n.c 11 dq8 95 dq40 53 n.c 137 n.c 12 vss 96 vss 54 vss 138 vss 13 dq9 97 dq41 55 dq16 139 dq48 14 dq10 98 dq42 56 dq17 140 dq49 15 dq11 99 dq43 57 dq18 141 dq50 16 dq12 100 dq44 58 dq19 142 dq51 17 dq13 101 dq45 59 vcc 143 vcc 18 vcc 102 vcc 60 dq20 144 dq52 19 dq14 103 dq46 61 n.c 145 n.c 20 dq15 104 dq47 62 n.c 146 n.c 21 n.c 105 n.c 63 cke1 147 n.c 22 n.c 106 n.c 64 vss 148 vss 23 vss 107 vss 65 dq21 149 dq53 24 n.c 108 n.c 66 dq22 150 dq54 25 n.c 109 n.c 67 dq23 151 dq55 26 vcc 110 vcc 68 vss 152 vss 27 /we 111 /cas 69 dq24 153 dq56 28 dqmb0 112 dqmb4 70 dq25 154 dq57 29 dqmb1 113 dqmb5 71 dq26 155 dq58 30 /cs0 114 /cs1 72 dq27 156 dq59 31 n.c 115 /ras 73 vcc 157 vcc 32 vss 116 vss 74 dq28 158 dq60 33 a0 117 a1 75 dq29 159 dq61 34 a2 118 a3 76 dq30 160 dq62 35 a4 119 a5 77 dq31 161 dq63 36 a6 120 a7 78 vss 162 vss 37 a8 121 a9 79 clk2 163 clk3 38 a10 122 a11 ( ba0 ) 80 n.c 164 n.c 39 n.c 123 n.c 81 wp 165 sa0 40 vcc 124 vcc 82 sda 166 sa1 41 vcc 125 clk1 83 scl 167 sa2 42 clk0 126 n.c 84 vcc 168 vcc pin name function pin name function vcc power suppl y ( 3.3v ) /we write enable vss ground ( 0v ) dqmb# data input/output mask clk# s y stem clock dq# data input/output /cs# chip select wp write protect cke# clock enable sda data i/o for spd a0-a10 address scl clk input for spd a11 bank select address sa# socket position address for spd /ras row address strobe n.c no connection /cas column address strobe
MSC23S4641E-8BS16 (98.06.22) serial presence detect byte no. spd hex value remark notes 0 80 defines the number of bytes written into spd memory 128 byte 1 08 total number of bytes of spd memory 256 byte 2 04 fundamental memory type sdram 3 0b number of rows 11 rows 4 09 number of columns 9 columns 5 02 number of module banks 2 bank 6 40 data width of this assembly 64 bits 7 00 ... data width conti nuation 0 8 01 voltage interface level lvttl 9 80 cycle time (cl=3) cl=3 tcc=8ns 10 60 access time from clk (cl=3) cl=3 tac3=6ns 11 00 dimm configuration type non parity 12 80 refresh rate / type normal/ self/ 13 08 primary sdram width x8 14 00 error checking sdram width 15 01 minimum clk delay tccd: 1 clk 16 8f burst lengths supported 1,2,4,8,f 17 02 number of banks on each sdram 2 banks 18 06 /cas latency 2,3 19 01 /cs latency 0 20 01 /we latency 0 21 00 sdram module attributes 22 06 sdram device attributes : general 23 c0 cycle time (cl=2) cl=2 tcc2=12ns 24 a0 access time from clk (cl=2) cl=2 tac2=10ns 25 00 cycle time (cl=1) not support 26 00 access time from clk (cl=1) not support 27 14 minimum row pulse width trp=20ns 28 14 /ras to /ras bank delay trrd=20ns 29 14 /ras to /cas delay trcd=20ns 30 30 minimum /ras precharge time tras=48ns 31 04 density of each bank on module 16mb 32 20 command and address signal input setup time 2ns 33 10 command and address signal input hold time 1ns 34 20 data signal input setup time 2ns 35 10 data signal input hold time 1ns 36-61 00-00 r.f.u 62 12 spd data revision code 1.2 63 2d checksum for byte 0-62 64-71 41,45,20,20,20,20,20,20 manufacturers jedec id code 72 01/06 manufacturing location 73-90 43,32,33,53,34,36,34,31,45, 2d , 38 , 42 , 53 , 31 , 36 , 20 , 20 , 20 manufacturers part number c23s4641e-8bs16 91,92 20,20 revision code 93-125 00-00 r.f.u 126 64 intel specification frequency 100mhz 127 f5 intel specification /cas latency clk0-3,cl=3 128-255 ff-ff unused storage locations
MSC23S4641E-8BS16 (98.06.22) electrical characteristics absolute maximum ratings rating symbol value unit voltage on any pin relative to vss v in , v out -0.5 to vcc+0.5 v vcc supply voltage vcc,vccq -0.5 to 4.6 v storage temperature t stg - 55 to 125 c power dissipation p d* 16 w short circuit current ios 50 ma operating temperature t opr 0 to 70 c *: ta=25 u recommended operating conditions (voltages referenced to vss = 0v) parameter symbol min. typ. max. unit power supply voltage vcc,vccq 3.0 3.3 3.6 v input high voltage vih 2.0 - vcc+0.3 v input low voltage vil -0.3 - 0.8 v capacitance (vcc=3.3v 0.3v, ta = 25c f=1mhz) parameter symbol max. unit input capacitance(a0-a11,/ras, /cas,/we) cin1 98 pf input capacitance(/cs0,/cs1,/cs2,/cs3) cin2 34 pf input capacitance(dqmb0-dqmb7) cin3 22 pf input capacitance(cke0,cke1) cin4 58 pf i/o c apacitance(dq0-dq63) c dq 25 pf input capacitance(clk0,clk1,clk2,clk3) c clk 50 pf
MSC23S4641E-8BS16 (98.06.22) dc characteristics (vcc = 3.3v 0.3v, ta = 0 to 70c) parameter symbol condition module spec. unit note bank cke others min max input leakage current i li - - - -160 160 ua output leakage current i lo -- - -20 20 ua output high voltage v oh -- i oh = -2ma 2.4 - v output low voltage v ol - - i ol = 2ma - 0.4 v average power supply current icc1 one bank active cke 3 vih tcc=min trc=min no burst - 1000 ma 1,2 (operating) icc1d both banks active cke 3 vih tcc=min trc=min trrd=min no burst - 1240 ma 1,2 power supply current (stand by) i cc2 both banks precharge cke 3 vih tcc=min - 640 ma 3 average power supply current (clock suspenson) i cc3s both banks active cke vil tcc=min - 344 ma 2 average power supply current (active stand by) i cc3 one banks active cke 3 vih tcc=min - 680 ma 3 power supply current (burst) i cc4 both banks a ct iv e cke 3 vih tcc=min - 1160 ma 1,2 power supply current (auto-refresh) icc5 one bank active cke 3 vih tcc=min trc=min - 960 ma 2 average power supply current (self-refresh) i cc6 both banks precharge cke vil tcc=min -32 ma average power supply current (power down) i cc7 both banks precharge cke vil tcc=min -32 ma note: 1. measured with the output open. 2. the address and data can be changed once or left uncharged during one cycle. 3. the address and data can be changed once or left unchanged during two cycles.
MSC23S4641E-8BS16 (98.06.22) mode set address keys /cas latenc y burst t y pe burst len g th a6 a5 a4 cl a3 bt a2 a1 a0 bt=0 bt=1 0 0 0 reserved 0 se q uential 0 0 0 1 1 0 0 1 reserved 1 interleave 0 0 1 2 2 0102 0104 4 0113 0118 8 1 0 0 reserved 1 0 0 reserved reserved 1 0 1 reserved 1 0 1 reserved reserved 1 1 0 reserved 1 1 0 reserved reserved 1 1 1 reserved 1 1 1 full pa g e reserved note: a7,a8,a9, a10 and a11 should stay "l" during mode set cycle. power on sequence 1. with inputs in nop state, turn on the power supply and start the system clock. 2. after the v cc voltage has reached the specified level,pause for 200us or more with the input kept in nop state. 3. issue the precharge all bank command. 4. apply a cbr auto-refresh eight or more times. 5. enter the mode register setting command.
MSC23S4641E-8BS16 (98.06.22) ac characteristic (vcc = 3.3 0.3v, ta = 0 ~70c) note 1,2 . parameter symbol m odule spec. unit note min. max. clock cycle time cl=3 tcc 8 - ns cl=2 12 - ns access time from clock cl=3 tac - 6 ns 3,4 cl=2 - 10 ns 3,4 clock "h" pulse time tch 3 - ns clock "l" pulse time tcl 3 - ns input setup time(clk,add,din) tsi 2 - ns input hold time(clk,add,din) thi 1 - ns output low impedance time from clock tolz 3 - ns output high impedance time from clock tohz - 9 ns output hold from clock toh 3 - ns /ras cycle time trc 70 - ns /ras precharge time trp 20 - ns /ras active time tras 48 100,000 ns /ras to /cas delay time trcd 20 - ns write recovery time twr 8 - ns write command input time from output towd 20 - ns /ras to /ras bank active delay time trrd 20 - ns refresh time tref - 64 ms power-down exit set-up time tpde 10 - ns input level transition time tt - 3 ns /cas to /cas delay time (min) iccd 1 cycle clock disable time from cke icke 1 cycle data output high impedance time from dqm idoz 2 cycle data input mask time from dqmb idod 0 cycle data input time from write command idwd 0 cycle data output high inpedance time iroh cl cycle active command input time from mode imrd 3 cycle notes: 1) ac measurements assume that tt=1ns. 2) the reference level for timing of input signals is 1.4v. 3) this parameter is measured with a load circuit equivalent to 1 ttl load and 50pf (r load is 50ohm). 4) an access time is measured at 1.4v. 5) if tt is longer than 1ns, the reference level for timing of input signals are v ih and v il. output 50pf output load 50 w 1.4v
MSC23S4641E-8BS16 (98.06.22) function truth table (table1)(1/2) current state /cs /ras /cas /we ba addr action idle h x x x x x nop lhhhxxnop l h h l ba x illegal 2 l h l x ba ca illegal 2 l l h h ba ra row active l l h l ba a10 nop 4 l l l h x x auto-refresh or self-refresh 5 l l l l l op code mode register write row active h x x x x x nop lhhxxxnop l h l h ba ca,a10 read lhllbaca,a10write l l h h ba ra illegal 2 l l h l ba a10 precharge lllxxxillegal read h x x x x x nop(continue row active after burst ends) l h h h x x nop(continue row active after burst ends) l h h l ba x reserved l h l h ba ca,a10 term burst,start new burst read l h l l ba ca,a10 term burst,start new burst write l l h h ba ra illegal 2 l l h l ba a10 term burst,execute row precharge lllxxxillegal write h x x x x x nop(continue row active after burst ends) l h h h x x nop(continue row active after burst ends) l h h l ba x illegal 2 l h l h ba ca,a10 term burst,start new burst read l h l l ba ca,a10 term burst,start new burst write l l h h ba ra illegal 2 l l h l ba a10 term burst,execute row precharge lllxxxillegal read with h x x x x x nop(continue burst to end and enter row precharge) auto precharge l h h h x x nop(continue burst to end and enter row precharge) l h h l ba x illegal 2 l h l h ba ca,a10 illegal 2 l h l l x x illegal l l h x ba ra,a10 illegal 2 lllxxxillegal write with h x x x x x nop(continue burst to end and enter row precharge) auto precharge l h h h x x nop(continue burst to end and enter row precharge) l h h l ba x illegal 2 l h l h ba ca,a10 illegal 2 l h l l x x illegal l l h x ba ra,a10 illegal 2 lllxxxillegal
MSC23S4641E-8BS16 (98.06.22) function truth table (table1)(2/2) current state /cs /ras /cas /we ba addr action precharge h x x x x x nop ? idle after trp lhhhxxnop ? idle after trp l h h l ba x illegal 2 l h l x ba ca illegal 2 l l h h ba ra illegal 2 l l h l ba a10 nop 4 lllxxxillegal write h x x x x x nop recovery l h h h x x nop l h h l ba x illegal 2 l h l x ba ca illegal 2 l l h h ba ra illegal 2 l l h l ba a10 illegal 2 lllxxxillegal row active h x x x x x nop row active after trcd l h h h x x nop row active after trcd l h h l ba x illegal 2 l h l x ba ca illegal 2 l l h h ba ra illegal 2 l l h l ba a10 illegal 2 lllxxxillegal refresh h x x x x x nop ? idle after trc lhhxxxnop ? idle after trc l h l x x x illegal l l h x x x illegal lllxxxillegal mode resister h x x x x x nop access l h h h x x nop l h h l x x illegal l h l x x x illegal l l x x x x illegal abbreviations ra=row address ba=bank address nop=no operation command ca=column address ap=auto precharge notes: 1. all inputs will be enabled when cke is set high for at least 1 cycle prior to the inputs. 2. illegal to bank in specified state,but may be legal in some cases depending on the state of bank selection. 3. satisfy the timing of tccd and twr to prevent bus contention. 4. nop to bank precharging or in idle state. precharges activated bank by ba or a10. 5. illegal if any bank is not idle.
MSC23S4641E-8BS16 (98.06.22) function truth table (cke) (table2) current state(n) cken-1 cken /cs /ras /cas /we addr action self refresh h x x x x x x invalid l h h x x x x exit self refresh ? abi l h l h h h x exit self refresh ? abi l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop(maintain self refresh) power down h x x x x x x invalid l h h x x x x exit power down ? abi l h l h h h x exit power down ? abi l h l h h l x illegal l h l h l x x illegal l h l x x x x illegal 6 l l x x x x x nop(continue power down mode) all banks idle 6 h h x x x x x refer to table 1 (abi) h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l h l x illegal h l l l l h x enter self refresh h l l l l l x illegal llxxxxxnop any state h h x x x x x refer to operations in table 1 other than h l x x x x x begin clock suspend next cycle listed above l h x x x x x enable clock of next cycle l l x x x x x continue clock suspension notes: 6. power-down and self refresh can be entered only when all the banks are in an idle state.

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